1. Field of the Invention
The present invention relates to a clock monitoring apparatus, particularly to a clock monitoring apparatus controlling a main clock and a sub clock to substitute for each other in failure to thereby realize a stable operation of a microcomputer even when the main clock is stopped.
2. Description of the Prior Art
Although a monitoring circuit of a clock is used for realizing a stable operation of a microcomputer, when a main clock is stopped, CPU is also stopped and therefore, it is requested for the monitoring circuit to monitor the clock by a signal stably operating even when the main clock is stopped and, when the main clock is stopped, to swiftly deal therewith.
In order to meet the request, it has been proposed that when the main clock is stopped, the stop of the clock is dealt with by switching the main clock to a sub clock as disclosed in, for example, a prior application (Single chip microcomputer: Japanese Patent Laid-Open No. 7-6155) and a method disclosed in the prior art literature is shown in FIG. 12.
In a circuit shown in FIG. 12, it is assumed that a main clock 1102 selected by a system clock switching circuit 1009 is oscillated normally. A timer 1004 is for counting a sub clock 1101 and during a time period in which the main clock 1102 is normally oscillated, the sub clock 1101 is reset periodically before overflowing by a timer reset signal 1105 outputted from an internal bus 1201 by receiving execution of instruction in CPU. Therefore, the timer 1004 is not overflowed and therefore, a timer carry signal 1106 is not issued.
When the main clock 1102 is stopped, since the timer reset signal 1105 is not issued, the timer is overflowed, the timer carry signal 1106 is issued and a clock switch flag 1006 is changed. Thereby, a clock switch signal 1108 is issued and the main clock 1102 is switched to the sub clock 1101.
As described above, according to the prior art, when the main clock is stopped for some cause, the stop is dealt with by switching the main clock to the sub clock and there is not provided a constitution of spontaneously issuing a reset signal and initializing the clock as in the present invention. Therefore, when the main clock is stopped, the main clock is switched to the sub clock which continues operating in a state as it is and there is a drawback that in order to recover an original state, a control or the like by a software is separately needed. Further, since the normally-counted signal is the sub clock, much time is needed until the counter overflows, as a result, there also poses a problem of producing time lag until the stop is deal with (switch to sub clock). When the sub clock is stopped, the abnormal stop cannot be detected.
It is an object of the present invention to provide a clock monitoring apparatus capable of automatically initializing a main clock when the main clock is stopped and continuing operation in a state before abnormality when the main clock is recovered, continuing operation by switching the main clock to a sub clock when the main clock cannot be recovered and issuing a flag when the sub clock is also stopped to thereby achieve stable operation of a microcomputer even when the main clock is stopped.
According to an aspect of the invention, there is provided a clock monitoring apparatus comprising a main clock monitoring portion including a first counter for counting a main clock, issuing a normal operation confirming flag indicating that a normal operation is being carried out when the first counter is overflowed or reaches a previously determined set value, monitoring the normal operation confirming flag by a sub clock, issuing a first main clock stop flag having an output in correspondence with H (high level)/L (low level) of the normal operation confirming flag and a main clock initializing signal for initializing the main clock when the main clock is determined to stop and resetting the first main clock stop flag when the main clock is recovered by receiving the main clock initializing signal, and a sub clock switching control portion including a second counter for counting a signal output produced by calculating a logical sum of the sub clock and the first main clock stop flag at fall of the sub clock at a time point of generating the first main clock stop flag, switching to a sub clock operation by issuing a sub clock switching signal when a second counter output is overflowed or reaches a previously determined set value and resetting the second counter output when the main clock is recovered and a second main clock stop flag produced by inverting the first main clock stop flag and delaying the sub clock by a predetermined period by a main clock monitoring portion, is reset.